1. Field of the Invention
The present invention relates to a phase locked loop (PLL), and more particularly, to a process-insensitive self-biasing PLL circuit and a self-biasing method thereof.
2. Description of the Related Art
A PLL circuit compares the phase of an input clock signal with the phase of an output clock signal to make the phases of the two signals correspond with each other. The PLL circuit is frequently used in a semiconductor integrated circuit such as a memory. Particularly, a self-biasing PLL circuit is used to secure loop. stability over a wide frequency range. A conventional self-biasing PLL circuit is disclosed in “A 0.4-4 Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs” described in “IEEE Journal of Solid State Circuits, Vol. 38, No. 5, pp. 747-754, May 2003”.
FIG. 1 is a block diagram of a conventional self-biasing PLL circuit. Referring to FIG. 1, the conventional self-biasing PLL circuit includes a phase frequency detector 11, a main charge pump circuit 12, an auxiliary charge pump circuit 13, a loop filter capacitor Cp, a first operational amplifier 14, a second operational amplifier 15, a voltage-controlled oscillator 16, a duty corrector 17, a divider 18, and a bias circuit 19.
In FIG. 1, ICLK represents an input clock signal, and FCLK denotes a feedback clock signal generated by frequency division by the divider 18. UP and DN respectively represent an up signal and a down signal generated by the phase frequency detector 11 to control the charge pump circuits 12 and 13.
In the conventional self biasing PLL circuit having the aforementioned configuration, the bandwidth of the loop is determined in proportion to an operating frequency. That is, the loop bandwidth is increased as the operating frequency is increased, but is decreased as the operating frequency is decreased. Furthermore, the position of loop zero used for loop stability is moved in proportion to the loop bandwidth.
It is important to maintain the proportional relationship of the operating frequency, loop bandwidth and loop zero for stability of the PLL circuit. To maintain the proportional relationship, the self-biasing circuit controls bias currents of the main charge pump circuit 12, the auxiliary charge pump circuit 13, the first operational amplifier 14, and the second operational amplifier 15 on the basis of a control voltage Vc with respect to the voltage-controlled oscillator 16. In other words, the bias circuit 19 generates a bias current In in response to the control voltage Vc corresponding to the output voltage of the second operational amplifier 15 and provides the bias current In as the bias currents of the main charge pump circuit 12, the auxiliary charge pump circuit 13, the first operational amplifier 14 and the second operational amplifier 15.
In the conventional self-biasing PLL circuit shown in FIG. 1, however, the bias circuit 19 is configured to generate the bias current In using only an NMOS transistor. Accordingly, loop stability is deteriorated because the position of loop zero is not proportional to the loop bandwidth when the NMOS transistor characteristic and the PMOS transistor characteristic are varied in different directions due to variations in semiconductor fabrication process conditions.
The problem of the conventional self-biasing PLL circuit will now be explained in more detail.
The frequency Fvco of the voltage-controlled oscillator 16 of the conventional self-biasing PLL circuit is represented by Equation 1, the loop bandwidth LOOP BW is represented by Equation 2, and loop zero LOOP ZR is represented by Equation 3.Fvco=a1(gmn+gmp)/C  [Equation 1]LOOP BW=Ipmp*Kvco/Gm =a2(gmn+gmp)  [Equation 2]LOOPZR =Gm/C=a3*gmn  [Equation 3]
Here, gmn and gmp denote transconductances of an NMOS transistor and a PMOS transistor included in the voltage-controlled oscillator 16, respectively. Ipmp represents the current of the main charge pump circuit 12, which is proportional to gmn, and Gm denotes transconductance of the first operational amplifier 14, which is also proportional to gmn. In addition, a1, a2 and a3 denote proportional factors.
From Equations 1, 2 and 3, it can be known that the frequency Fvco of the voltage-controlled oscillator 16 and the loop bandwidth LOOP BW are proportional to the sum of gmn and gmp but loop zero LOOP ZR is proportional to only gmn in the conventional self-biasing PLL circuit.
When NMOS transistor characteristics and PMOS transistor characteristics are varied in the same direction in a semiconductor fabrication process, for example, when both operating speeds of NMOS and PMOS transistors are increased or decreased, the aforementioned proportional relationship is maintained. However, when the NMOS transistor characteristics and PMOS transistor characteristics are varied in different directions in the semiconductor fabrication process, for example, when the operating speed of the NMOS transistor is increased while the operating speed of the PMOS transistor is decreased or when the operating speed of the NMOS transistor is decreased while the operating speed of the PMOS transistor is increased, the aforementioned proportional relationship may not be maintained. In this case, loop stability is deteriorated to cause an erroneous operation of the self-biasing PLL circuit in a worst case scenario.
As described above, the conventional self-biasing PLL circuit is sensitive to a variation in the semiconductor fabrication process and thus loop stability may be deteriorated depending on the process circumstances.